IRQ – Interrupt Request
Interrupt Requests or IRQs are interrupts that are raised by hardware devices. Some devices generate an IRQ when they have data ready to be read, or when they finish a command eg : writing the content of buffer to the disk. In short, a device for example, from sound card to network card, mouse, keyboard, serial ports etc will generate an IRQ whenever it wants the processor’s attention.
PIC – Programmable Interrupt Controllers
Any IBM PC/AT Compatible computer has 2 chips that are used to manage IRQs. These chips are called PIC. One acts as a master IRQ controller and another one acts as a slave IRQ controller. The slave is connected to IRQ2 on the master controller, whereas master controller is directly connected to the processor itself. Each PIC can handle 8 IRQs. Master PIC handles IRQ0 to IRQ7 and slave IRQ handles IRQ8 to IRQ15.Whenever a device signals an IRQ, the CPU pauses whatever it was doing and calls the ISR to handle the corresponding IRQ. The CPU then performs whatever actions were required and tells the PIC that the CPU has finished executing the correct routine.
PIT – Programmable Interval Timer
The programmable Interval Timer(PIT) is also called the System Clock, is a chip used for generating interrupts at regular time intervals. It has 3 channels. Channel 0 is mapped to IRQ0 and is used to interrupt the CPU at predictable and regular times. Channel 1 is system specific and Channel 2 is connected to the system speaker and is used in order to make computer beep. Out of three, main Channels to be considered are Channel 0 and 2. Channel 0 allows to accurately schedule new processes later on, as well as allow the current task to wait for certain period of time.
Reference : Bran’s Kernel Development Tutorial
IDT – Interrupt Descriptor Table
The IDT is used to show the processor what Interrupt Service Routine (ISR) to call to handle an exception. IDT entries are also called Interrupt requests whenever a device has completed a request and needs to be serviced. IDT entries are similar to GDT entries. Both have base address, access flag and both are 64 bits long. The main difference lies in the meanings of the address fields. In an IDT, the base address is the address of ISR that the processor should call when this interrupt is called. An IDT entry doesn’t have a limit, instead it has a segment that need to be specified. The segment is the same as located ISR. This will allow the processor to pass on the control to the kernel through an interrupt that has occurred when the processor is in a different ring like when an application is running.
ISR – Interrupt Service Routine
ISRs are used to save the current processor state and set up the appropriate segment registers needed for kernel mode before the kernel’s C-level interrupt handler is called. To handle the right exception, the correct entry in the IDT should be pointed to the correct ISR. An exception is a special case that the processor encounters when it cannot continue the normal execution. For example when dividing by zero, the result is unknown, thus the processor will throw an exception and kernel will stop that process avoiding any problems. If the processor finds that the program is trying to access a piece of memory that it shouldn’t, it will cause the General Protection Fault.
Some exceptions push an error code onto the stack. Thus to decrease the complexity, a dummy error code of 0 is pushed onto the stack for any ISR that doesn’t push an error code already. This is done to keep a uniform stack frame. To track the exception, the interrupt number is also pushed on to the stack. The assembler opcode ‘cli’ is used to disable the interrupts and prevent an IRQ (Interrupt Request) from firing, which could cause the conflicts in our kernel. To protect the kernel, each ISR is made to jump to ‘isr_common_stub’. The assembler opcode ‘isr_common_stub’ will save the processor state on the stack, push the current stack address onto the stack, call the ‘fault_handler’ function and finally restore the state of the stack.
Reference : Bran’s Kernel Development Tutorial.
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