Registers in 32 bit and 64 bit Architecture

After reading Bran’s kernel tutorial and understanding the design of most basic kernel development, it was time for me to begin my real work, i.e the implementation of 64 bit kernel. Thus to begin with, I started reading the different types of registers available in both 32 bit and 64 bit Architecture. Well without wasting much time, let me go though it quickly.

There are following four types of Registers.

1. General Purpose Registers

2. Segment Registers

3. Program Status and Control Register

4. Instruction Pointer Register

1. General Purpose Registers

In 32 bit, 8 general purpose registers are EAX, EBX, ECX, EDX, ESI, EDI, EBP and ESP.

In 64 bit, there 64 bit 16 general purpose registers and default operand size is 32 bit.Registers RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP and R8-R15 are available.

All of them serve the following purpose :

Operands for logical and arithmetic operation, Operands for address calculation and Memory pointers.

2. Segment Register

In 32 bit, there are 6 segment registers. They are, CS, DS, SS, ES, FS and GS. They are all 16 bit segment selectors, which points to the particular segment in memory. A particular segment can be accessed by the corresponding segment selector which has to present in an appropriate segment register. Each of the segment registers is associated with one of the three  types of storages: code, data or stack. CS registers mainly points to code segment. DS, ES, FS and GS register points to data segment and SS register points to Stack segment.

In 64 bit mode, CS, DS, ES, SS are  treated  as if each  segment base is 0, regardless of the value of the associated segment descriptor base. This creates a flat address space for code, data and stack. FS and GS are exception and both are used as additional base registers in linear address calculations.

3. Program Status and Control Register

The 32 bit EFLAGS registers contain the group of status flags, a control flag and a group of system flags.

Status flag: bits 0, 2, 4, 6, 7 and 11 are the status flags and they indicate the result of any arithmetic instructions.

Direction flag(DF) : The direction flag(bit 10) controls string instructions eg: MOVS, CMPS, SCAS, LODS and STOS). Setting up the DF flag causes the string instruction to auto increment whereas clearing the DF flag causes the string instruction to auto decrement. STD and CLD instruction sets and clear the DF flag, respectively.

Apart from above, there are few flags which control the operating system and should not be modified by the application.

In 64 bit mode, EFLAGS is extended to 64 bits and are called RFLAGS. The upper 32 bits of RFLAGS are reserved and the lower 32 bits are same as the EFLAGS.

4. Instruction Pointer Register

Instruction Pointer register contains the offset in the current code segment for the next instruction to be executed. It cannot be accessed directly by the software. It is controlled implicitly by control transfer instructions like JMP, JCC, CALL and RET.

In 32 bit mode, instruction pointer is EIP which is 32 bits long and in 64 bit mode, instruction pointer is 64 bits long and named as RIP.

Reference : Intel and AMD Manuals.